Lateral double-diffused metal-oxide-semiconductor (LDMOS) transistors are commonly used in high-voltage applications (20 to 500 volts) because of their high breakdown voltage characteristics and compatibility with low voltage CMOS technology. In general, an N-type LDMOS transistor includes a polysilicon gate, an N+ source region formed in a P-type body region, and an N+ drain region. The N+ drain region is separated from the channel formed in the body region under the polysilicon gate by an N drift region. It is well known that by increasing the length of the N-drift region, the breakdown voltage of the LDMOS transistor can be accordingly increased.
FIG. 1 is a cross-sectional diagram showing an existing LDMOS device 100 provided as a high voltage N-channel Lateral DMOS (LDMOS). It is noted that this type of device can be formed in an N-type epitaxial layer, a P-type epitaxial layer or a P-type substrate. The N-channel LDMOS device 100 formed in either an epitaxial layer or a P-type substrate 110 includes a N+ source region 120 disposed in a P-well body region 112 and a N+ drain contact pickup region 122 disposed in N-drift drain region 114. A P+ body pickup region 124 is also formed on a top portion of the P-well body region 112 laterally adjacent to the source region 120. A field oxide (FOX) 116 is formed on a top portion of the N-drift drain region 114 right next to the drain contact pickup region 122 and an insulated gate 118 disposed on top of the P-well body region 112 and the N-drift drain region 114 extends from overlapping a portion of the source region 120 to overlapping a portion of the field oxide 116. The insulated gate 118 is electrical insulated from the substrate 110 by a thin gate oxide (not shown). An active channel 126 is formed in the P-well body region underneath the gate 118 from the source region 120 to the P-N junction between the P-well body region 112 and the N-drift drain region 114 and an accumulation region 128 is region formed in the N-drift drain region 114 underneath the gate 118 from the PN junction to the first end of the field oxide 116 closer to the PN junction.
The existing N channel LDMOS with butting P-well body region and lightly doped N-drift drain region as described above may have poor quasi-saturation, poor hot carrier injection (HCI) performance and/or high RdsON.
It is within this context that embodiments of the present invention arise.